Floating Gate of Flash Memory Device and Method of Forming the Same

ABSTRACT

Disclosed is a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.11/647,021, filed Dec. 27, 2006, pending, which is incorporated hereinby reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a floating gate and a method of formingthe same.

2. Description of the Related Art

A flash memory is a kind of nonvolatile memory. Applications of theflash memory have been extended, and a chip integration density of theflash memory has also been improved.

Products in which a flash memory is embedded in a general logic havebeen applied in various fields. Accordingly, it is a problem to reducemanufacturing costs and power consumption.

To reduce manufacturing costs, a chip size must be reduced and a processmust be simplified. However, the chip size has been currently reduceddown to 0.10 μm with the rapid development of a photo process inaccordance with a design rule.

Further, production costs can be reduced not only by simplifying aprocess but also by eliminating a process in which failure may occur inview of a yield.

Meanwhile, in a design of a flash memory device, a floating gaterequires high capacitance for the purpose of coupling a higher floatinggate voltage from a control gate.

As a method for obtaining high capacitance as described above, there aremethods of increasing an overlap between floating and control gates,utilizing a material with an interlayer dielectric constant, reducingthe thickness of an interlayer dielectric layer, and the like.

The method of utilizing a material with an interlayer dielectricconstant or reducing the thickness of an interlayer dielectric layer hasa disadvantage in that a leakage current is large.

Therefore, the method of increasing an overlap between floating andcontrol gates is mainly used to obtain high capacitance. However, themethod of increasing an overlapping area has a disadvantage in that acell area is increased.

As a method for solving these disadvantages, there is a method ofincreasing an overlapping area of a sidewall rather than that of a plan,which causes many problems in view of planarization.

One of such area increasing methods is a method of allowing the shape ofa floating gate to be uneven.

That is, there is a method in which a floating gate is primarily formed,and a mask process is then performed such that the interior of thefloating gate is removed by a predetermined thickness, thereby allowingthe shape of the floating gate to be uneven.

In this case, the capacitance of a floating gate is increased inaccordance with the increase of an area due to unevenness, and thus thecoupling ratio of a flash memory is increased.

However, there is a problem in that a mask process must be performedtwice in such a method, i.e., a process is complicated and manufacturingcosts are increased.

SUMMARY OF THE INVENTION

The present invention has been made to solve the above mentioned problemoccurring in the prior art, and it is an object of the present inventionto provide a floating gate of a flash memory device and a method offorming the same, wherein the area of the floating gate is extended, anda coupling ratio is increased.

According to one aspect of the present invention, there is provided afloating gate of a flash memory device, wherein a tunneling oxide layeris formed on a semiconductor substrate, and a floating gate is formed inthe shape of a lens having a convex top surface.

According to another aspect of the present invention, there is provideda method of forming a floating gate in a flash memory device, whichincludes the steps of: forming a tunneling oxide layer on asemiconductor substrate; forming a conductive layer on the tunnelingoxide layer; coating a photoresist layer on the conductive layer andthen selectively patterning the photoresist layer, thereby defining afloating gate area; selectively removing the conductive layer by apredetermined thickness from a top surface of the conductive layer byusing the patterned photoresist layer as a mask; performing a thermalprocess with respect to the photoresist layer, thereby, reflowing thephotoresist layer with the shape of a lens having a convex top surface;and simultaneously etching the photoresist layer subjected to reflowingand the conductive layer, thereby forming a floating gate with the shapeof a lens having a convex top surface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing a floating gate of a flash memorydevice according to the present invention; and

FIGS. 2A to 2E are sectional views illustrating a process of forming afloating gate in a flash memory device according to the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a floating gate of a flash memory device and a method offorming the same according to the present invention will be described indetail with reference to the accompanying drawings.

FIG. 1 is a sectional view showing a floating gate of a flash memorydevice according to the present invention.

As shown in FIG. 1, a tunneling oxide layer 102 is formed on asemiconductor substrate 101, and a floating gate is formed in the shapeof a lens having a convex top surface.

FIGS. 2A to 2E are sectional views illustrating a process of forming afloating gate in a flash memory device according to the presentinvention.

As shown in FIG. 2A, a tunneling oxide layer 102 is formed in athickness of 80 to 120 Å on a semiconductor substrate 101, and apoly-silicon layer 103 is formed in a thickness of 900 to 1100 Å on thetunneling oxide layer 102.

Here, the poly-silicon 103 may be formed by allowing the thickness ofthe poly-silicon layer 103 to be adjusted depending on etchingselectivity with a photoresist layer to be coated later.

As shown in FIG. 2B, a photoresist layer 104 is coated on an entiresurface of the semiconductor substrate 101 having the poly-silicon layer103, and the photoresist layer 104 is selectively patterned through anexposure and development process, thereby defining a floating gate area.

Here, after the photoresist layer 104 has been coated, an antireflectivecoating (not shown) may be formed in a thickness of about 600 Å.

Meanwhile, in a method of coating the photoresist layer 104, there aremethods of spin coat, spray coat, dip coat and the like. However, thespin coat performed while chucking and rotating a wafer at a high speedunder a vacuum atmosphere is advantageous to stability and uniformity.

Then, a photo mask (not shown) corresponding to a desired pattern ispositioned on the photoresist layer 104, and a photoresist pattern isthen formed to have a desired size through exposure and developmentprocesses.

Here, the development process is performed through deposition orspraying. In the former, it is difficult to manage a temperature, adensity, a change in time and the like, while, in the latter, it isrelatively easy to manage. Currently, an apparatus subjected to in-linethrough a spraying scheme has been widely used.

As shown in FIG. 2C, the poly-silicon layer 103 is selectively removedby a predetermined thickness from a top surface thereof by using thepatterned photoresist layer 104 as a mask.

Here, the thickness of the poly-silicon layer 103 removed by thepredetermined thickness is about ½ of the original thickness of thepoly-silicon layer 103.

As shown in FIG. 2D, a thermal process is performed with respect to thephotoresist layer 104 such that the photoresist layer 104 is subjectedto reflowing, thereby forming a photoresist layer 104 a with the shapeof a lens having a convex top surface.

As shown in FIG. 2E, the photoresist layer 104 subjected to reflowingand the residual poly-silicon layer 103 are simultaneously etched atetching selectivity of 1:1, thereby forming a floating gate 105 with theshape of a lens having a convex top surface.

Subsequently, after the floating gate 105 has been formed, the residualphotoresist layer 104 and impurities are removed, and a washing processis performed.

As described above, a floating gate of a flash memory device and amethod of forming the same according to the present invention hasadvantages as follows.

That is, a floating gate is formed in the shape of a lens having aconvex top surface through a simple process, so that the area of thefloating gate can be extended, and a coupling ratio can be increased.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the present invention. Thus,it is intended that the present invention covers the modifications andvariations thereof within the scope of the appended claims.

1. A floating gate of a flash memory device, comprising: a tunnelingoxide layer on a semiconductor substrate; a floating gate having a lensshape and a convex top surface; a gate oxide on the floating gate; and aconcave control gate on the gate oxide.
 2. The nonvolatile memory deviceof claim 1, wherein the gate oxide and the control gate have a shapecomplementary to that of the floating gate.
 3. The nonvolatile memorydevice of claim 1, wherein the gate oxide and the control gate also havea shape effective to increase the capacitance or coupling ratio betweenthe floating gate and the control gate, relative to an otherwiseidentical nonvolatile memory having a planar floating gate.
 4. Thenonvolatile memory device of claim 1, wherein the floating gate has awidth of from 45 nm to 150 nm.
 5. The nonvolatile memory device of claim4, wherein the floating gate width is less than or equal to 100 nm. 6.The nonvolatile memory device of claim 2, wherein the control gate has awidth greater than that of the floating gate, and portions of thefloating gate extend along sidewalls of the floating gate.
 7. Anonvolatile memory device, comprising: a tunnel oxide layer on asemiconductor substrate; a floating gate on the tunnel oxide layerhaving a convex top surface; a gate oxide on the floating gate; and acontrol gate on the gate oxide.
 8. The nonvolatile memory device ofclaim 8, wherein the floating gate has a shape effective to increase acapacitance or a coupling ratio between the floating gate and thecontrol gate.
 9. The nonvolatile memory device of claim 9, wherein thegate oxide and the control gate have a shape complementary to that ofthe floating gate.
 10. The nonvolatile memory device of claim 8, whereinthe gate oxide and the control gate also have a shape effective toincrease the capacitance or coupling ratio between the floating gate andthe control gate, relative to an otherwise identical nonvolatile memoryhaving a planar floating gate.
 11. The nonvolatile memory device ofclaim 8, wherein the floating gate has a width of from 45 nm to 150 nm.12. The nonvolatile memory device of claim 12, wherein the floating gatewidth is less than or equal to 100 nm.
 13. The nonvolatile memory deviceof claim 9, wherein the control gate has a width greater than that ofthe floating gate, and portions of the floating gate extend alongsidewalls of the floating gate.